1. Field of the Invention
The present invention relates generally to processing systems, and more specifically to multi-core processing systems.
2. Background Art
Multi-processor System on Chips (MPSoC) are often favored for applications requiring high performance while maintaining a particular cost and power consumption budget. Unfortunately, effectively harnessing the power available to MPSoCs often requires very complex programming techniques to fully utilize the wide variety of hardware resources that may be available to the programmer, which may include multi-core processors, custom DSP chips, DMA engines, memory chips, and other components. Moreover, concurrent code execution on separate hardware resources introduces issues of I/O dependencies and task synchronization that are difficult to resolve and optimize without having a deep understanding of the hardware components and their various interrelations.
More specifically, MPSoC programmers are faced with the non-trivial tasks of 1) task partitioning, or breaking up a large high-level monolithic application into smaller tasks that can be run in parallel, 2) application mapping, or determining where each specific function or task is to be executed, for example to which particular processor of the various types that may be available, 3) task scheduling, or determining when each specific function or task is to be executed, for example, a task can only be executed when an available processor is available and this specific task has no pending data dependencies.
To assist application programmers and designers in task partitioning, application mapping, and task scheduling of high-level application code for MPSoCs, various MPSoC tools and techniques for automated scheduling have been developed. While such automated task scheduling techniques may provide acceptable results without additional edits, manual adjustments through an application profiler or visualizer may still be necessary to provide the best possible performance and to meet application requirements for real-time processing.
However, existing tools available for MPSoC profiling and visualization are often difficult to use, focusing on very low level hardware elements while failing to provide a broad, high level view of all processes occurring within the MPSoC. Accordingly, application designers and programmers often fail to appreciate the impact of their programming decisions on total execution time, which may result in the application failing to meet real-time timing requirements. For example, a base station application processing LTE signals may require incoming frames of data to be processed before a certain deadline to avoid buffer under-runs and other errors. If application designers and programmers fail to optimize the LTE processing application to meet those deadlines, the application may fail to operate as intended.
Accordingly, there is a need to overcome the drawbacks and deficiencies in the art by providing a framework that facilitates a high level understanding of MPSoC application code for facilitated profiling and optimization and at the same time allow for specific and low level profiling of an application running on a designated MPSoC.